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EDA Transistor Level Timing Methodologist - Lead / Architect (5-10 yrs.)

Location:	Bangalore
Education:	BE (8+Yrs ) / ME (6+Yrs ) / Phd (5+Yrs) ...in Electrical Engineering/Computer Science/Physics
No. of Positions:	2
Business Group:	Asic / Vlsi / Soc / Chip / EDA
Industry:	Semiconductor Jobs
Approx Hiring time in weeks:	10

Target Project/Product Details

The EDA and ASIC Methodology team works closely with the EDA team in the US for EDA software development in the areas of physical design automation, timing closure, power, extraction, system level design automation, as well as providing support and education to the design teams.

Company Profile

The Trend Setting Product Company, Known through most of its recent history as the world's largest company, with over 4, 00,000 employees worldwide. It has engineers and consultants in over 170 countries and has eight Research laboratories worldwide.   The Component Solutions offering of the Engineering & Technology Services (E&TS) has three major groups working on VLSI Chip Design, Circuit Design and Electronic Design Automation (EDA).The EDA and ASIC Methodology team works closely with the EDA team in the US for EDA software development in the areas of physical design automation, timing closure, power, extraction, system level design automation, as well as providing support and education to the design teams. Our client in India is a rapidly growing organization. Working in E&TS Component Solutions gives an engineer the opportunity to work directly with the best design teams in the world, and enables access to world-class fabrication process knowledge, and world-renowned EDA research and development team, a depth and breadth of technology which is unparalleled and unmatched by any company in the world. Innovation is encouraged leading to significant number of patents.

Skills

Key Skills:Array Design Experience , TCL, Skill, Perl, C++ , Static Timing ,Circuits ,UNIX
Must have Skills: Signal integrity or macro inter-coupling analysis development. Tool performance improvement in collaboration with simulation development team. Simulation model validation, regression testing.
Good to have Skills: Transistor Level Timing Methodologist .

Roles and Responsibilities

Being a part of 3 people team supporting array timing methodology for server customers. Review array designs, put customized TLT support, maintain design environment, and support array designers. Opportunity to work daily with state-of-art array designs, and define critical timing methodology. Very tight working relationship with array design leads/managers .  Signal integrity or macro inter-coupling analysis development. Tool performance improvement in collaboration with simulation development team. Simulation model validation, regression testing .

Contact Details

Company Name: Largest semiconductor & EDA Employer in World
Contact Email: leela@handigital.com